1. Field of the Invention
The present invention relates to a MOS (metal oxide semiconductor) type semiconductor device having an ESD (electrostatic discharge) protection arrangement, which is constituted such that an internal circuit of the MOS type semiconductor device is protected from damage caused by ESD phenomena, and more particularly, to an improvement of such an ESD protection arrangement including a plurality of MOS transistors.
2. Description of the Related Art
In order to protect an internal circuit of a MOS type semiconductor device from damage caused by ESD phenomena, an ESD protection arrangement is provided in the MOS type semiconductor device.
As discussed in detail hereinafter, the provision of the ESD protection arrangement involves both an uneven snapback-occurrence problem and a latch-up problem, and these problems must be solved before the ESD protection arrangement can be properly operated. However, it is difficult to simultaneously solve both the uneven snapback-occurrence problem and the latch-up problem because there is a tradeoff relationship therebetween.
For example, in JP-A-H11-274404 disclosing a MOS type semiconductor device having an ESD protection arrangement, although a solution of the uneven snapback-occurrence problem is discussed, there is no reference to occurrence of the latch-up problem.